General Description

The 5T93GL04 2.5V differential clock buffer is a user-selectable

differential input to four LVDS outputs. The fanout from a differential

input to four LVDS outputs reduces loading on the preceding driver

and provides an efficient clock distribution network. The 5T93GL04

can act as a translator from a differential HSTL, eHSTL, LVEPECL

(2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A

single-ended 3.3V / 2.5V LVTTL input can also be used to translate

to LVDS outputs. The redundant input capability allows for a

glitchless change-over from a primary clock source to a secondary

clock source up to 450MHz. Selectable inputs are controlled by SEL.

During the switchover, the output will disable low for up to three clock

cycles of the previously-selected input clock. The outputs will remain

low for up to three clock cycles of the newly-selected clock, after

which the outputs will start from the newly-selected input. A FSEL

pin has been implemented to control the switchover in cases where

a clock source is absent or is driven to DC levels below the minimum

specifications.

The IDT5T93GL04 outputs can be asynchronously

enabled/disabled. When disabled, the outputs will drive to the value

selected by the GL pin. Multiple power and grounds reduce noise.

• Guaranteed low skew: <50ps (maximum)

• Very low duty cycle distortion: <100ps (maximum

• High speed propagation delay: <2.2ns (maximum)

• Up to 450MHz operation

• Selectable inputs

• Hot insertable and over-voltage tolerant inputs

• 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL

(3.3V), CML or LVDS input interface

• Selectable differential inputs to four LVDS outputs

• Power-down mode

• At power-up, FSEL should be LOW

• 2.5V VDD

• -40°C to 85°C ambient operating temperature

• Available in TSSOP package

• Recommends IDT5T9304 if glitchless input selection is not

required

• Not Recommended for New Designs

• For functional replacement use 8SLVD1204