CY7C1339价格

参考价格:¥26.3182

型号:CY7C1339G-133AXC 品牌:Cypress 备注:这里有CY7C1339多少钱,2024年最近7天走势,今日出价,今日竞价,CY7C1339批发/采购报价,CY7C1339行情走势销售排行榜,CY7C1339报价。
型号 功能描述 生产厂家&企业 LOGO 操作

128Kx32SynchronousPipelinedCacheRAM

FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

128Kx32SynchronousPipelinedCacheRAM

FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

128Kx32SynchronousPipelinedCacheRAM

FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

128Kx32SynchronousPipelinedCacheRAM

FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

128Kx32SynchronousPipelinedCacheRAM

FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

128Kx32SynchronousPipelinedCacheRAM

FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

128Kx32SynchronousPipelinedCacheRAM

FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

128Kx32SynchronousPipelinedCacheRAM

FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

128Kx32SynchronousPipelinedCacheRAM

FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

128Kx32SynchronousPipelinedCacheRAM

FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

128Kx32SynchronousPipelinedCacheRAM

FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-Mbit(128Kx32)PipelinedSyncSRAM

FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features •

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

4-MBIT(128KX32)PIPELINEDSYNCSRAM

FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

CY7C1339产品属性

  • 类型

    描述

  • 型号

    CY7C1339

  • 制造商

    Rochester Electronics LLC

  • 功能描述

    - Bulk

更新时间:2024-6-4 19:22:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
2017+
QFP
6528
只做原装正品假一赔十!
CYPRESS
831
297
原装正品长期供货,如假包赔包换 徐小姐13714450367
Cypress
21+
100TQFP (14x20)
13880
公司只售原装,支持实单
Cypress
23+
100TQFP (14x20)
9000
原装正品,支持实单
CYPRESS
17+
NA
9988
全新原装现货,请联系18721787578唐先生
CYP
2339+
N/A
5650
公司原厂原装现货假一罚十!特价出售!强势库存!
Cypress
2021+
QFP
5003
原装正品假一罚十
CYPRESS
17+
TQFP-100
2500
原装现货热卖
Cypress
23+
100-LQFP
7750
全新原装优势
CypressSemiconductorCorp
2022
ICSRAM4MBIT100MHZ100LQFP
5058
原厂原装正品,价格超越代理

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