Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

GeneralDescription TheHC2509Cisalow-skew,lowjitter,phase-lockedloop(PLL)clockdriver,distributinghighfrequencyclocksignalsforSDRAM. Features ●Phase-LockedLoopClockDistributionforSynchronousDRAMApplications ●SupportsPC-100andMeets“PC100SDRAMregisteredDIMMSpecif

Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

GeneralDescription TheHC2510Cisalow-skew,lowjitter,phase-lockedloop(PLL)clockdriver,distributinghighfrequencyclocksignalsforSDRAM Features ●Phase-LockedLoopClockDistributionforSynchronousDRAMApplications ●SupportsPC-100andMeets“PC100SDRAMregisteredDIMMSpecifi

Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

GeneralDescription TheHC2510Cisalow-skew,lowjitter,phase-lockedloop(PLL)clockdriver,distributinghighfrequencyclocksignalsforSDRAM Features ●Phase-LockedLoopClockDistributionforSynchronousDRAMApplications ●SupportsPC-100andMeets“PC100SDRAMregisteredDIMMSpecifi

Dual 4-Input Data Selector/Multiplexer with 3-State Otputs

TheSL74HC253isidenticalinpinouttotheLS/ALS253.ThedeviceinputsarecompatiblewithstandardCMOSoutputs;withpullupresistors,theyarecompatiblewithLS/ALSTTLoutputs. TheAddressInputsselectoneoffourDataInputsfromeachmultiplexer.Eachmultiplexerhasanactive-lowOutput

QUAD 2 CHANNEL MULTIPLEXER 3-STATE

DESCRIPTION The74VHC257isanadvancedhigh-speedCMOSQUAD2-CHANNELMULTIPLEXER(3-STATE)fabricatedwithsub-micronsilicongateanddouble-layermetalwiringC2MOStechnology. ■HIGHSPEED:tPD=3.7ns(TYP.)atVCC=5V ■LOWPOWERDISSIPATION:ICC=4µA(MAX.)atTA=25°C ■HIGHNOISEI

QUAD 2-CHANEL MULTIPLEXER (3-STATE)

Quad 2-Input Data Selector/Multiplexer with 3-State Outputs

TheSL74HC257isidenticalinpinouttotheLS/ALS257.ThedeviceinputsarecompatiblewithstandardCMOSoutputs;withpullupresistors,theyarecompatiblewithLS/ALSTTLoutputs. Thisdeviceselectsa(4-bit)nibblefromeithertheAorBinputsasdeterminedbytheSelectinput.Thenibblei

Quad. 2-to-1-line Data Selectors/Multiplexers(with noninverted 3-state outputs)

Description Thelargeoutputdrivecapabilitycoupledwiththe3-statefeaturemakethisdeviceidealforinterfacingwithbuslinesinabusorganizedsystem.Whentheoutputcontrolinputlineistakenhigh,theoutputsofallfourmultiplexersaresentintoahighimpedancestate.Whentheout

Hybrid Coupler 3 dB, 90o

文件：1.64997 Mbytes Page：9 Pages

Hybrid Coupler 3 dB, 90o

文件：1.54908 Mbytes Page：9 Pages

Hybrid Coupler 3 dB, 90o

文件：1.45699 Mbytes Page：9 Pages

Hybrid Coupler 3 dB, 90o

文件：1.44816 Mbytes Page：9 Pages

90 Degree Hybrid 2.30 GHz-2.65 GHz

文件：746.48 Kbytes Page：4 Pages

90 Degree Hybrid 2.30 GHz-2.65 GHz

文件：401.52 Kbytes Page：5 Pages

Quartz SMD, Ceramic

文件：174.11 Kbytes Page：1 Pages

Quartz SMD, Ceramic

文件：174.11 Kbytes Page：1 Pages

包装：散装 描述：TAPE,LONG LEADER 3/8\ 工具 专用工具

包装：散装 描述：TAPE,LONG LEADER 3/8\ 工具 专用工具

High Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs

文件：52.16 Kbytes Page：7 Pages

Hybrid Coupler 3 dB, 90o

文件：2.14767 Mbytes Page：9 Pages